Design of BiCMOS SRAMs for high‐speed SiGe applications-Reference-Cited by-同舟云学术

Design of BiCMOS SRAMs for high‐speed SiGe applications

Published:2014-11 Issue:6 Volume:8 Page:487-498
ISSN:1751-858X
Container-title:IET Circuits, Devices & Systems
language:en
Short-container-title:IET Circuits, Devices & Systems

Author:

Liu Xuelian¹,LeRoy Mitchell R.¹,Clarke Ryan¹,Chu Michael¹,Aquino Hadrian O.¹,Raman Srikumar¹,Zia Aamir¹,Kraft Russell P.¹,McDonald John F.¹

Affiliation:

1. Electrical, Computer & Systems Engineering DepartmentRensselaer Polytechnic Institute110 8th street, CII‐6015TroyNY12180USA

Funder

National Science Foundation

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Control and Systems Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cds.2013.0375

Reference39 articles.

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2. A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management

3. Hamzaoglu F. Zhang K. Wang Y. et al.: ‘A 153Mb‐SRAM design with dynamic stability enhancement and leakage reduction in 45 nm high‐k metal‐gate CMOS technology’.2008 IEEE Int. Solid‐State Circuits Conf. Digest of Technical Papers (ISSCC) February2008 pp.376–377

4. SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction

5. Zhang K. Bhattacharya U. Ma L. et al.: ‘A fully synchronized pipelined and re‐configurable 50 Mb SRAM on 90 nm CMOS technology for logic applications’.2003 Symp. on VLSI Circuits Digest of Technical Papers June2003 pp.253–254