A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry-Reference-Cited by-同舟云学术

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A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry

Published:2013-01 Issue:1 Volume:48 Page:150-158
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Karl Eric,Wang Yih,Ng Yong-Gee,Guo Zheng,Hamzaoglu Fatih,Meterelliyoz Mesut,Keane John,Bhattacharya Uddalak,Zhang Kevin,Mistry Kaizad,Bohr Mark

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/6399535/06381488.pdf?arnumber=6381488

Cited by 47 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Novel Zigzag SRAM Bitcell Design in the Complementary FET Framework;IEEE Transactions on Electron Devices;2023-09

2. Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-08

3. Based on the comparison with other kinds of storage devices to predict the future development of STT-MRAM;Highlights in Science, Engineering and Technology;2023-04-25

4. Voltage Boosted Fail Detecting Circuit for Selective Write Assist and Cell Current Boosting for High-Density Low-Power SRAM;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-02

5. FPSNET: An Architecture for Neural-Network-Based Feature Point Extraction for SLAM;Electronics;2022-12-13

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