Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K-Reference-Cited by-同舟云学术

Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K

Author:

Parihar Shivendra Singh¹^ORCID,van Santen Victor M.¹^ORCID,Thomann Simon¹^ORCID,Pahwa Girish²^ORCID,Chauhan Yogesh Singh³^ORCID,Amrouch Hussam⁴^ORCID

Affiliation:

1. Semiconductor Test and Reliability (STAR) Research Group, University of Stuttgart, Stuttgart, Germany

2. Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA

3. Department of Electrical Engineering, NANOLAB, Indian Institute of Technology (IIT) Kanpur, Kanpur, India

4. AI Processor Design, Technical University of Munich (TUM), Munich, Germany

Funder

Swarna Jayanti Fellowship

Deutsche Forschungsgemeinschaft (DFG) AM 534/3-1

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Link

Reference41 articles.

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