A 4.24-GHz 128×256 SRAM Operating Double Pump Read Write Same Cycle in 5-nm Technology
Author:
Affiliation:
1. Memory Solution Division, Taiwan Semiconductor Manufacturing Company North America, San Jose, CA, USA
2. Memory Solution Division, Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, Taiwan
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8011414/10359146/10328755.pdf?arnumber=10328755
Reference10 articles.
1. A 6.05-Mb/mm216-nm FinFET double pumping 1W1R 2-port SRAM with 313 ps read access time
2. A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low VMIN applications
3. 2RW dual-port SRAM design challenges in advanced technology nodes
4. A 5.92-Mb/mm2 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry
5. A 0.094um2 high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV VMIN with read and write assist
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1. Revolutionizing Semiconductor Technology: A Comprehensive Review of FinFET;2024 International Conference on Communication, Computer Sciences and Engineering (IC3SE);2024-05-09
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