A 6.05-Mb/mm216-nm FinFET double pumping 1W1R 2-port SRAM with 313 ps read access time-Reference-Cited by-同舟云学术

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A 6.05-Mb/mm216-nm FinFET double pumping 1W1R 2-port SRAM with 313 ps read access time

Published:2016-06 Issue: Volume: Page:
ISSN:
Container-title:2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)
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Author:

Yabuuchi Makoto,Sawada Yohei,Sano Toshiaki,Ishii Yuichiro,Tanaka Shinji,Tanaka Miki,Nii Koji

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7569797/7573453/07573460.pdf?arnumber=7573460

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 4.13-GHz UHS Pseudo Two-Port SRAM With BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4-nm FinFET Technology;IEEE Journal of Solid-State Circuits;2024-04

2. 2.2 “Zen 4c”: The AMD 5nm Area-Optimized ×86-64 Microprocessor Core;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18

3. 15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18

4. A 4.24-GHz 128×256 SRAM Operating Double Pump Read Write Same Cycle in 5-nm Technology;IEEE Solid-State Circuits Letters;2024

5. A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2018-11

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