A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS

Author:

Chan Chi-Hang,Zhu Yan,Chio U-Fat,Sin Sai-Weng,Seng-Pan U.,Martins R. P.

Publisher

IEEE

Cited by 38 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A 2.5 GHz, 0.6 V Body Driven Dynamic Comparator Exploiting Charge Pump Based Dynamic Biasing;2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME);2023-06-18

2. Low Power and High Speed Charge Pump based Dual Stage Dynamic Comparator using 45nm CMOS Technology;2023 8th International Conference on Communication and Electronics Systems (ICCES);2023-06-01

3. An RRAM-based building block for reprogrammable non-uniform sampling ADCs;it - Information Technology;2023-05-01

4. Modify two stage OPAMP based on offset constellation technique;AIP Conference Proceedings;2023

5. Resolution-Selective and Resolution-Adaptive 2 to 8-Bit Flash ADC for High-Speed Application-Independent IC (HS-AIIC);Journal of Circuits, Systems and Computers;2022-03-24

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