Low Power and High Speed Charge Pump based Dual Stage Dynamic Comparator using 45nm CMOS Technology-Reference-Cited by-同舟云学术

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Low Power and High Speed Charge Pump based Dual Stage Dynamic Comparator using 45nm CMOS Technology

Published:2023-06-01 Issue: Volume: Page:
ISSN:
Container-title:2023 8th International Conference on Communication and Electronics Systems (ICCES)
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Author:

K Brindha¹,J Manjula¹

Affiliation:

1. SRMIST,Department of ECE,Chennai,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10192571/10192589/10192627.pdf?arnumber=10192627

Reference30 articles.

1. An 8-bit 150-MHz CMOS A/D converter

2. The StrongARM Latch [A Circuit for All Seasons]

3. Voltage Comparator With 60% Faster Speed by Using Charge Pump

4. A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time

5. Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A high‐speed and power efficient CMOS dynamic comparator for data converter circuits;International Journal of Numerical Modelling: Electronic Networks, Devices and Fields;2024-06-26

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