A 2.5 GHz, 0.6 V Body Driven Dynamic Comparator Exploiting Charge Pump Based Dynamic Biasing
Author:
Affiliation:
1. Sapienza University Of Rome,Via Eudossiana 18,Italy,00184
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10161731/10161695/10161910.pdf?arnumber=10161910
Reference15 articles.
1. A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS
2. A low-offset latched comparator using zero-static power dynamic offset cancellation technique
3. Low-power 600 MHz comparator for 0.5 V supply voltage in 0.12 [micro sign]m CMOS
4. A 30fJ/comparison dynamic bias comparator
5. An 8.5mW 5GS/s 6b flash ADC with dynamic offset calibration in 32nm CMOS SOI;chen;2013 Symposium on VLSI Circuits VLSIC,2013
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Body Biasing Techniques for Dynamic Comparators: A Systematic Survey;Electronics;2024-02-09
2. An Improved Strong Arm Comparator With Integrated Static Preamplifier;IEEE Access;2023
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