An Improved Strong Arm Comparator With Integrated Static Preamplifier
Author:
Affiliation:
1. Department of Information Engineering, Electronics and Telecommunications, Sapienza University of Rome, Rome, Italy
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
General Engineering,General Materials Science,General Computer Science,Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/6287639/10005208/10229118.pdf?arnumber=10229118
Reference15 articles.
1. A Back-Gate-Input Clocked Comparator with Improved Speed and Reduced Noise in 22-nm SOI CMOS
2. Dual Time-Interleaved Successive Approximation Register ADCs for an Ultra-Wideband Receiver
3. A novel high-speed low-power dynamic comparator with complementary differential input in 65 nm CMOS technology
4. A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture
5. A 2.5 GHz, 0.6 V Body Driven Dynamic Comparator Exploiting Charge Pump Based Dynamic Biasing
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