A novel high-speed low-power dynamic comparator with complementary differential input in 65 nm CMOS technology

Author:

Ghasemian Hossein,Ghasemi Razieh,Abiri Ebrahim,Salehi Mohammad Reza

Publisher

Elsevier BV

Subject

General Engineering

Reference20 articles.

1. Design of Analog CMOS Integrated Circuits;Razavi,2001

2. A 7.65-mW 5-bit 90-nm 1-Gs/s folded interpolated ADC without calibration;D’Amico;IEEE Trans. Instrum. Meas.,2014

3. A 12-b 10-GS/s interleaved pipeline ADC in 28-nm CMOS technology;Devarajan;IEEE J. Solid State Circuits,2017

4. 26.7 A 2.6 b/cycle-architecture-based 10b 1 JGS/s 15.4 mW 4×-time-interleaved SAR ADC with a multistep hardware-retirement technique;Hong,2015

5. Digital background calibration for pipelined ADCs based on comparator decision time quantization;Ragab;IEEE Trans. Circuits Syst. Part II: Express Briefs,2015

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