A low-power, low-offset, and power-scalable comparator suitable for low-frequency applications
Author:
Affiliation:
1. CSIR- Central Electronics Engineering Research Institute (CEERI), Pilani, Rajasthan, India
2. Academy of Scientific and Innovative Research (AcSIR), Ghaziabad- 201002, India
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering
Link
https://www.tandfonline.com/doi/pdf/10.1080/00207217.2023.2246710
Reference54 articles.
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2. AlMarashli, A., Anders, J., & Ortmanns, M. (2016). A hybrid comparator for high resolution sar adc. in 2016 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, pp. 1050–1053.
3. Baker, R. J. (2008). CMOS: Mixed-signal circuit design. john Wiley & sons.
4. An ultra high-speed high-resolution low-offset low-power voltage comparator with a reliable offset cancellation method for high-performance applications in 0.18 µm CMOS technology
5. A low-power 12-bit SAR ADC for remote pressure measurement
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