Automated Design of a Strong-ARM Dynamic Comparator-Reference-Cited by-同舟云学术

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Automated Design of a Strong-ARM Dynamic Comparator

Published:2024-05-10 Issue: Volume: Page:171-176
ISSN:
Container-title:2024 2nd International Symposium of Electronics Design Automation (ISEDA)
language:
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Author:

Jiang Jiaquan¹,Wu Qingsen²,Wang Yuan³,Qin Qian³,Hao Jinglei³,Chai Chenkai³,Lu Yukai³,Huang Jiwen²,Li Lin²,Ye Zuochang³

Affiliation:

1. National Innovation Platform for the Fusion of Industry and Education in Integrated Circuits,Xiamen,China

2. School of Electronic Science and Engineering, Xiamen University,Xiamen,China

3. School of Integrated Circuits Tsinghua University,Beijing,China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10616249/10617469/10617721.pdf?arnumber=10617721

Reference12 articles.

1. Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques

2. A new high-speed low-power and low-offset dynamic comparator with a current-mode offset compensation technique

3. A 2.4-GS/s Power-Efficient, High-Resolution Reconfigurable Dynamic Comparator for ADC Architecture

4. Kickback noise reduction techniques for CMOS latched comparators

5. Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator

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