A 2.4-GS/s Power-Efficient, High-Resolution Reconfigurable Dynamic Comparator for ADC Architecture

Author:

Raut Gopal,Shah Ambika Prasad,Sharma Vishal,Rajput Gunjan,Vishvakarma Santosh KumarORCID

Funder

UGC-DAE Consortium for Scientific Research, University Grants Commission

Publisher

Springer Science and Business Media LLC

Subject

Applied Mathematics,Signal Processing

Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design and Analysis of a Power-Efficient Dynamic Comparator with an Improved Transconductance in Ultra-low Power SAR ADC Applications;Circuits, Systems, and Signal Processing;2024-08-13

2. Automated Design of a Strong-ARM Dynamic Comparator;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10

3. 45nm CMOS Two-Stage Latched Comparator;2022 International Conference on Smart Systems and Power Management (IC2SPM);2022-11-10

4. Loading Effect Free MOS-only Voltage Reference Ladder for ADC in RRAM-crossbar Array;Proceedings of the Great Lakes Symposium on VLSI 2022;2022-06-06

5. Functional validation of highly synthesizable voltage comparator on FPGA;Integration;2022-05

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