An offset cancellation technique for comparators using body-voltage trimming

Author:

Babayan-Mashhadi Samaneh,Lotfi Reza

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Reference12 articles.

1. Razavi, B., & Wooley, B. A. (1992). Design techniques for high-speed, high-resolution comparators. IEEE Journal of solid state circuits, 27(12).

2. Van der Plas, G., Decoutere, S., & Donnay, S. (2006). A 0.16pJ/conversion-Step 2.5 mW 1.25 GS/s 4b ADC in a 90 nm digital CMOS process. In IEEE ISSCC on digestive technology papers, San Francisco.

3. Verbruggen, B., Craninckx, J., Kuijk, M., Wambacq, P., & Van der Plas, G. (2008). A 2.2 mW 5b 1.75 GS/s folding flash ADC in 90 nm digital CMOS. In IEEE ISSCC on digestive technology papers (pp. 252–253).

4. Chan, C. H., Zhu, Y., Chio, U. F., Sin, S. W., & Martins, R. P. (2009). A voltage-controlled capacitance offset calibration technique for high resolution dynamic comparator. In International SoC design conference (ISOCC) (pp. 392–395, Issue 22–24).

5. Yao, J., Liu, J., & Lee, H. (2010). Bulk voltage trimming offset calibration for high-speed flash ADCs. IEEE Transactions on Circuits and Systems II Express Briefs, 57(2), 110–114.

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