1. A 9-bit 150-MS/s subrange ADC based on SAR architecture in 90-nm CMOS;Lin;IEEE Trans Circuits Syst I Reg Papers,2013
2. A SAR-assisted two-stage pipeline ADC;Lee;IEEE J Solid-State Circuits,2011
3. Analog integrated circuit design;Johns,1997
4. A double-tail latch-type voltage sense amplifier with 18ps setup+hold time;Schinkel,2007
5. A low-offset latched comparator using zero-static power dynamic offset cancellation technique;Miyahara,2009