0.45-mW 2.35-3.0 GHz Multiplying DLL with Calibration Loop in 28nm CMOS FD-SOI
Author:
Affiliation:
1. STMicroelectronics,Crolles,France
2. Univ. Bordeaux, Bordeaux INP, UMR CNRS,IMS Laboratory,Talence,France,5218
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10268677/10268683/10268768.pdf?arnumber=10268768
Reference9 articles.
1. A 0.0056mm2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and −249dB FOM
2. A 0.5V-to-0.9V 0.2GHz-to-5GHz Ultra-Low-Power Digitally-Assisted Analog Ring PLL with Less Than 200ns Lock Time in 22nm FinFET CMOS Technology
3. A Fractional-N Synthesizable PLL Using DTC-Based Multistage Injection With Dithering-Assisted Local Skew Calibration
4. 25.5 A Self-Calibrated 1.2-to-3.8GHz 0.0052mm2 Synthesized Fractional-N MDLL Using a 2b Time-Period Comparator in 22nm FinFET CMOS
5. A 265-?W Fractional-N Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and DutyCycled Frequency-Locked Loop in 65-nm CMOS;liu;IEEE JSSC 2019,0
Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Fast Settling Phase-Locked Loops: A Comprehensive Survey of Applications and Techniques [Feature];IEEE Circuits and Systems Magazine;2024
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