25.5 A Self-Calibrated 1.2-to-3.8GHz 0.0052mm2 Synthesized Fractional-N MDLL Using a 2b Time-Period Comparator in 22nm FinFET CMOS-Reference-Cited by-同舟云学术

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25.5 A Self-Calibrated 1.2-to-3.8GHz 0.0052mm2 Synthesized Fractional-N MDLL Using a 2b Time-Period Comparator in 22nm FinFET CMOS

Published:2020-02 Issue: Volume: Page:
ISSN:
Container-title:2020 IEEE International Solid- State Circuits Conference - (ISSCC)
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Author:

Kundu Somnath,Chai Likai,Chandrashekar Kailash,Pellerano Stefano,Carlton Brent

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9046640/9062887/09062939.pdf?arnumber=9062939

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An Injection-Locked Clock Multiplier with Adaptive Pulsewidth Adjustment and Phase Error Cancellation Achieving 43.9fs RMS Jitter and -255.5dB FoM;2024 IEEE Custom Integrated Circuits Conference (CICC);2024-04-21

2. Design of Synthesizable Digital Phase Locked Loops;IPSJ Transactions on System and LSI Design Methodology;2024

3. 0.45-mW 2.35-3.0 GHz Multiplying DLL with Calibration Loop in 28nm CMOS FD-SOI;ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC);2023-09-11

4. 14.1 A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving −67dBc Fractional Spur;2023 IEEE International Solid- State Circuits Conference (ISSCC);2023-02-19

5. A Fractional-N Synthesizable PLL Using DTC-Based Multistage Injection With Dithering-Assisted Local Skew Calibration;IEEE Journal of Solid-State Circuits;2022-10

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