A Fractional-N Synthesizable PLL Using DTC-Based Multistage Injection With Dithering-Assisted Local Skew Calibration

Author:

Xu Zule1ORCID

Affiliation:

1. Systems Design Lab, School of Engineering, The University of Tokyo, Tokyo, Japan

Funder

Japan Society for the Promotion of Science (JSPS) KAKENHI

VDEC, The University of Tokyo, in collaboration with Synopsys, Inc., Cadence Design Systems, Inc., and Mentor Graphics, Inc

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Reference35 articles.

1. 19.2 A 0.2-to-1.45GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detection

2. A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop

3. A Fractional-N Digital MDLL With Background Two-Point DTC Calibration

4. A fractional-N digital MDLL with background two-point DTC calibration achieving $-$60 dBc fractional spur;zhang;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2021

5. Injecting-time self-alignment achieving $-$270 dB FoM and $-$66 dBc reference spur;zhang;Proc Symp VLSI Circuits,2019

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design of Synthesizable Digital Phase Locked Loops;IPSJ Transactions on System and LSI Design Methodology;2024

2. 0.45-mW 2.35-3.0 GHz Multiplying DLL with Calibration Loop in 28nm CMOS FD-SOI;ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC);2023-09-11

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