A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop-Reference-Cited by-同舟云学术

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A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop

Published:2015-11 Issue:11 Volume:50 Page:2678-2691
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Levantino Salvatore^ORCID,Marucci Giovanni,Marzin Giovanni,Fenaroli Andrea,Samori Carlo,Lacaita Andrea L.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/7307914/07265103.pdf?arnumber=7265103

Cited by 49 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A high-pass shaped LMS algorithm based predistortion technique for fractional-N BB-DPLLs;Microelectronics Journal;2024-04

2. A low-jitter and low-phase noise switched-loop filter PLL using fast phase-error correction and dual-edge phase comparison technique;Integration;2024-01

3. Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration;IEEE Journal of Solid-State Circuits;2024-01

4. Design of Synthesizable Digital Phase Locked Loops;IPSJ Transactions on System and LSI Design Methodology;2024

5. Phase Noise Analysis for Stochastically Injected Oscillators;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-08

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