Design of Synthesizable Digital Phase Locked Loops
Author:
Affiliation:
1. Department of Electrical and Electronic Engineering, Tokyo Institute of Technology
Publisher
Information Processing Society of Japan
Link
https://www.jstage.jst.go.jp/article/ipsjtsldm/17/0/17_44/_pdf
Reference63 articles.
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2. [2] Shu, G. et al.: A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop, IEEE Journal of Solid-State Circuits, Vol.49, No.4, pp.1036-1047 (2014).
3. [3] Cao, C. et al.: A 50-GHz Phase-Locked Loop in 0.13-µm CMOS, IEEE Journal of Solid-State Circuits, Vol.42, No.8, pp.1649-1656 (2007).
4. [4] Park, J. et al.: 76-81-GHz CMOS Transmitter with a Phase-Locked-Loop-Based Multichirp Modulator for Automotive Radar, IEEE Trans. Microwave Theory and Techniques, Vol.63, No.4, pp.1399-1408 (2015).
5. [5] Chen, J. et al.: The Design of All-Digital Polar Transmitter Based on ADPLL and Phase Synchronized ΔΣ Modulator, IEEE Journal of Solid-State Circuits, Vol.47, No.5, pp.1154-1164 (2012).
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