A 0.0056mm2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and −249dB FOM
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8304413/8310156/08310212.pdf?arnumber=8310212
Cited by 17 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
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2. 0.45-mW 2.35-3.0 GHz Multiplying DLL with Calibration Loop in 28nm CMOS FD-SOI;ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC);2023-09-11
3. A Low-Phase-Noise Self-Aligned Sub-Harmonically Injection-Locked PLL Using Aperture Phase Detector-Based DLL Windowing Technique;IEEE Access;2023
4. A 97fsrms-Jitter and 68-Multiplication Factor, 8.16GHz Ring-Oscillator Injection-Locked Clock Multiplier with Power-Gating Injection-Locking and Background Multi-Functional Digital Calibrator;2022 IEEE International Solid- State Circuits Conference (ISSCC);2022-02-20
5. An N/M-Ratio All-Digital Clock Generator with a Pseudo-NMOS Comparator-Based Programmable Divider;Electronics;2022-01-14
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