1. A 0.2-2 GHz 12 mW multiplying DLL for low-jitter clock synthesis in highly-integrated data communication chips;Farjad-Rad,2002
2. A 2.4-GHz 1.5-mW digital multiplying delay-locked loop using pulsewidth comparator and double injection technique;Kim;IEEE J. Solid-State Circuits,2017
3. Clock multiplication techniques using digital multiplying delay-locked loops;Elshazly;IEEE J. Solid-State Circuits,2013
4. A 0.0056 mm2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3 mW block-sharing frequency tracking loop achieving 292fs rms Jitter and- 249dB FOM;Yang,2018
5. A 4.6 GHz MDLL with- 46dBc reference spur and aperture position tuning;Ali,2011