A Fractional-N Synthesizable PLL Using DTC-Based Multistage Injection With Dithering-Assisted Local Skew Calibration-Reference-Cited by-同舟云学术

A Fractional-N Synthesizable PLL Using DTC-Based Multistage Injection With Dithering-Assisted Local Skew Calibration

Published:2022-10 Issue:10 Volume:57 Page:2979-2987
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Xu Zule¹^ORCID

Affiliation:

1. Systems Design Lab, School of Engineering, The University of Tokyo, Tokyo, Japan

Funder

Japan Society for the Promotion of Science (JSPS) KAKENHI

VDEC, The University of Tokyo, in collaboration with Synopsys, Inc., Cadence Design Systems, Inc., and Mentor Graphics, Inc

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9900477/09825684.pdf?arnumber=9825684

Reference35 articles.

1. 19.2 A 0.2-to-1.45GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detection

2. A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop

3. A Fractional-N Digital MDLL With Background Two-Point DTC Calibration

4. A fractional-N digital MDLL with background two-point DTC calibration achieving $-$60 dBc fractional spur;zhang;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2021

5. Injecting-time self-alignment achieving $-$270 dB FoM and $-$66 dBc reference spur;zhang;Proc Symp VLSI Circuits,2019

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