A 0.5V-to-0.9V 0.2GHz-to-5GHz Ultra-Low-Power Digitally-Assisted Analog Ring PLL with Less Than 200ns Lock Time in 22nm FinFET CMOS Technology
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9060424/9075871/09075897.pdf?arnumber=9075897
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. An All Digital PLL in 22-nm FD SOI for Hardware Accelerated Embedded Systems;2024 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE);2024-08-06
2. Fast Settling Phase-Locked Loops: A Comprehensive Survey of Applications and Techniques [Feature];IEEE Circuits and Systems Magazine;2024
3. A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL;IEEE Open Journal of the Solid-State Circuits Society;2024
4. 0.45-mW 2.35-3.0 GHz Multiplying DLL with Calibration Loop in 28nm CMOS FD-SOI;ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC);2023-09-11
5. Design and Implementation of Third and Fourth Order Phase Lock Loop Using Simulink;Lecture Notes in Networks and Systems;2023
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