Author:
Xiang Bo,Fan Yongping,Ayers James,Shen James,Zhang Dan
Cited by
3 articles.
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1. 0.45-mW 2.35-3.0 GHz Multiplying DLL with Calibration Loop in 28nm CMOS FD-SOI;ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC);2023-09-11
2. Design and Implementation of Third and Fourth Order Phase Lock Loop Using Simulink;Lecture Notes in Networks and Systems;2023
3. A 0.0048mm2 0.43-to-1.0V 0.54-to-1.76GHz Bias-Current-Free PLL in 14nm FinFET CMOS;2021 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA);2021-11-24