D6CIM: 60.4-TOPS/W, 1.46-TOPS/mm<sup>2</sup>, 1005-Kb/mm<sup>2</sup> Digital 6T-SRAM-Based Compute-in-Memory Macro Supporting 1-to-8b Fixed-Point Arithmetic in 28-nm CMOS-Reference-Cited by-同舟云学术

D6CIM: 60.4-TOPS/W, 1.46-TOPS/mm², 1005-Kb/mm² Digital 6T-SRAM-Based Compute-in-Memory Macro Supporting 1-to-8b Fixed-Point Arithmetic in 28-nm CMOS

Published:2023-09-11 Issue: Volume: Page:
ISSN:
Container-title:ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC)
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Author:

Oh Jonghyun¹,Lin Chuan-Tung¹,Seok Mingoo¹

Affiliation:

1. Columbia University,Dept. of Electrical Engineering,New York,USA

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10268677/10268683/10268725.pdf?arnumber=10268725

Reference7 articles.

1. A Compact-Area Low-VDDmin 6T SRAM With Improvement in Cell Stability, Read Speed, and Write Margin Using a Dual-Split-Control-Assist Scheme

2. DIMC: 2219TOPS/W 2569F2/b Digital In-Memory Computing Macro in 28nm Based on Approximate Arithmetic Hardware

3. A 5-nm 254-TOPS/W 221-TOPS/mm 2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-VoltageFrequency Scaling and Simultaneous MAC and Write Operations;fujiwara;IEEE International Solid-State Circuits Conference (ISSCC),2022

4. A 1.041-Mb/mm² 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications

5. A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications

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1. iMCU: A 28-nm Digital In-Memory Computing-Based Microcontroller Unit for TinyML;IEEE Journal of Solid-State Circuits;2024-08

2. A 1–8b Reconfigurable Digital SRAM Compute-in-Memory Macro for Processing Neural Networks;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-04

3. PS-IMC: A 2385.7-TOPS/W/b Precision Scalable In-Memory Computing Macro With Bit-Parallel Inputs and Decomposable Weights for DNNs;IEEE Solid-State Circuits Letters;2024