PS-IMC: A 2385.7-TOPS/W/b Precision Scalable In-Memory Computing Macro With Bit-Parallel Inputs and Decomposable Weights for DNNs-Reference-Cited by-同舟云学术

PS-IMC: A 2385.7-TOPS/W/b Precision Scalable In-Memory Computing Macro With Bit-Parallel Inputs and Decomposable Weights for DNNs

Published:2024 Issue: Volume:7 Page:102-105
ISSN:2573-9603
Container-title:IEEE Solid-State Circuits Letters
language:
Short-container-title:IEEE Solid-State Circuits Lett.

Author:

Sridharan Amitesh¹^ORCID,Saikia Jyotishman²,Anupreetham ³,Zhang Fan¹^ORCID,Seo Jae-Sun³^ORCID,Fan Deliang¹^ORCID

Affiliation:

1. Department of Electrical and Computer Engineering, Johns Hopkins University, Baltimore, MD, USA

2. School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ, USA

3. School of Electrical and Computer Engineering, Cornell Tech, New York, NY, USA

Funder

National Science Foundation

CoCoSys in JUMP 2.0

DARPA

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

https://ieeexplore.ieee.org/ielam/8011414/10359146/10443989-aam.pdf

Reference8 articles.

1. A 5-nm 254-TOPS/W 221-TOPS/mm2 fully-digital computing-in-memory macro supporting wide-range dynamic-voltage-frequency scaling and simultaneous MAC and write operations;Fujiwara

2. A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications

3. An 89TOPS/W and 16.3TOPS/mm2 all-digital SRAM-based full-precision compute-in memory macro in 22nm for machine-learning edge applications;Chih

4. A 4nm 6163-TOPS/W/b 4790–TOPS/mm2/b SRAM based digital-computing-in-memory macro supporting bit-width flexibility and simultaneous MAC and weight update;Mori

5. DIMCA: An Area-Efficient Digital In-Memory Computing Macro Featuring Approximate Arithmetic Hardware in 28 nm