A Compact-Area Low-VDDmin 6T SRAM With Improvement in Cell Stability, Read Speed, and Write Margin Using a Dual-Split-Control-Assist Scheme
Author:
Funder
MOST of Taiwan
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4/8015205/07932845.pdf?arnumber=7932845
Cited by 23 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Negative capacitance FET based dual-split control 6T-SRAM cell design for energy efficient and robust computing-in memory architectures;Microelectronic Engineering;2024-05
2. eCIMC: A 603.1-TOPS/W eDRAM-Based Cryogenic In-Memory Computing Accelerator Supporting Boolean/Convolutional Operations;IEEE Journal of Solid-State Circuits;2024
3. CLUT-CIM: A Capacitance Lookup Table-Based Analog Compute-in-Memory Macro With Signed-Channel Training and Weight Updating for Nonuniform Quantization;IEEE Transactions on Circuits and Systems I: Regular Papers;2024
4. D6CIM: 60.4-TOPS/W, 1.46-TOPS/mm2, 1005-Kb/mm2 Digital 6T-SRAM-Based Compute-in-Memory Macro Supporting 1-to-8b Fixed-Point Arithmetic in 28-nm CMOS;ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC);2023-09-11
5. Dual Power Gating 8-Transistor SRAM Design For Low Power Applications;2023 International Conference on System Science and Engineering (ICSSE);2023-07-27
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