Signal Integrity(SI) aware HBM2e/3 interposer design approach considering y-axis offset between logic and HBM die for HPC/AI/Network applications
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/9501397/9501403/09501588.pdf?arnumber=9501588
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Signal Integrity Designs at Organic Interposer CoWoS-R for HBM3-9.2Gbps High Speed Interconnection of 2.5D-IC Chiplets Integration;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28
2. Efficient Investigation of Coupled Lines in Quasi Periodical High-Density Signal Routings for HPC Applications;2024 IEEE 28th Workshop on Signal and Power Integrity (SPI);2024-05-12
3. Multi-Stripline Redistribution Layer Interposer Channel Design for High Bandwidth Memory Module Considering Via Interconnect;2023 20th International SoC Design Conference (ISOCC);2023-10-25
4. 2.5D Large-Scale Interposer Bonding Process Verification using Daisy-Chain for PIM Heterogeneous Integration Platform;2023 International Conference on Electronics, Information, and Communication (ICEIC);2023-02-05
5. Transformer Network-Based Reinforcement Learning Method for Power Distribution Network (PDN) Optimization of High Bandwidth Memory (HBM);IEEE Transactions on Microwave Theory and Techniques;2022-11
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