Multi-Stripline Redistribution Layer Interposer Channel Design for High Bandwidth Memory Module Considering Via Interconnect-Reference-Cited by-同舟云学术

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Multi-Stripline Redistribution Layer Interposer Channel Design for High Bandwidth Memory Module Considering Via Interconnect

Published:2023-10-25 Issue: Volume: Page:247-248
ISSN:
Container-title:2023 20th International SoC Design Conference (ISOCC)
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Author:

Yoon Jiwon¹,Kim Hyunwoo¹,Sim Boogyo¹,Park Hyunwook²,Kim Yigyeong³,Park Sujin³,Kwon Youngsu³,Kim Joungho¹

Affiliation:

1. Korea Advanced Institute of Science and Technology (KAIST),School of Electrical Engineering,Daejeon,Republic of Korea

2. Missouri University of Science and Technology (MST),EMC Laboratory,Rolla,MO,USA

3. Electronics and Telecommunications Research Institute (ETRI),PIM AI HPU Group,Daejeon,Republic of Korea

Funder

National Research Foundation of Korea

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10395912/10395932/10396127.pdf?arnumber=10396127

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