Electrical Coupling Effect of Forksheet FET for Power, Performance, and Area Analysis

Author:

Lee Junjong1ORCID,Yoon Jun-Sik1ORCID,Lim Jaewan1,Baek Rock-Hyun1ORCID

Affiliation:

1. Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, Republic of Korea

Funder

Ministry of Trade, Industry, and Energy

National Research Foundation of Korea (NRF) grant funded by the Korea government

POSTECH-Samsung Electronics Industry-Academia Cooperative Research Center

BK21 FOUR Program

IC Design Education Center

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Reference25 articles.

1. A 10 nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, self-aligned quad patterning, contact over active gate and cobalt local interconnects;auth;IEDM Tech Dig,2017

2. Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm Node

3. Comparison of electrical performance of co-integrated forksheets and nanosheets transistors for the 2 nm technological node and beyond;ritzenthaler;IEDM Tech Dig,2021

4. CFET Design Options, Challenges, and Opportunities for 3D Integration

5. Performance, Power, and Area of Standard Cells in Sub 3 nm Node Using Buried Power Rail

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Parasitic Capacitance Model for Stacked Gate-All-Around Nanosheet FETs;IEEE Transactions on Electron Devices;2024-01

2. TCAD-Based Analysis of Nanosheet and Forksheet FET Electrical Characteristics in the Presence of Gamma and Heavy Ion Radiation;2023 11th International Symposium on Electronic Systems Devices and Computing (ESDC);2023-05-04

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