Unveiling the Role of Interface and Dielectric Wall Traps with Self-heating Induced Aging Prediction of Forksheet FET
Author:
Affiliation:
1. Indian Institute of Technology,Roorkee,India
2. Indian Institute of Technology,Bhubaneswar,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10511270/10511310/10511703.pdf?arnumber=10511703
Reference10 articles.
1. Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips
2. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET
3. Comparison of Electrical Performance of Co-Integrated Forksheets and Nanosheets Transistors for the 2nm Technological Node and Beyond
4. Trapping of Hot Carriers in the Forksheet FET Wall: A TCAD Study
5. Transistor aging and reliability in 14 nm tri-gate technology;Novak;IEEE IRPS,2015
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