CFET Design Options, Challenges, and Opportunities for 3D Integration
Author:
Affiliation:
1. TEL Technology Center, America, LLC,Albany,NY
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9720433/9720494/09720577.pdf?arnumber=9720577
Reference4 articles.
1. Agile Pathfinding Technology Prototyping: the Hunt for Directional Correctness
2. Standard cell architectures for N2 node: transition from FinFET to nanosheet and to forksheet device
3. The Complementary FET (CFET) for CMOS scaling beyond N3
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