Enhanced DFT for Fortuitous Detection of Transition Faults During Scan Shift
Author:
Affiliation:
1. Southern Methodist University,Lyle School of Engineering,Dallas,Texas, 75205
2. University of St. Thomas,School of Engineering,Saint Paul,Minnesota 55105
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9826869/9826902/09826976.pdf?arnumber=9826976
Reference18 articles.
1. Invisible delay quality - SDQM model lights up what could not be seen
2. On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults
3. SR-TPG: A low transition test pattern generator for test-per-clock and test-per-scan BIST
4. TestExpress - New Time-Effective Scan-Based Deterministic Test Paradigm
5. Test-per-clock testing of the circuits with scan
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