SR-TPG: A low transition test pattern generator for test-per-clock and test-per-scan BIST

Author:

Abu-Issa Abdallatif S.,Tumar Iyad K.,Ghanem Wasel T.

Publisher

IEEE

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Efficient weight-based segmentation of scan-chains using NLFSR;2023 IEEE 20th India Council International Conference (INDICON);2023-12-14

2. Harvesting Wasted Clock Cycles for Efficient Online Testing;2023 IEEE European Test Symposium (ETS);2023-05-22

3. Enhanced DFT for Fortuitous Detection of Transition Faults During Scan Shift;2022 IEEE 31st Microelectronics Design & Test Symposium (MDTS);2022-05-23

4. Analysis of Switching Activity in Various Implementation of Combinational circuit;2020 6th International Conference on Advanced Computing and Communication Systems (ICACCS);2020-03

5. Energy-Efficient Scheme for Multiple Scan-Chains BIST Using Weight-Based Segmentation;IEEE Transactions on Circuits and Systems II: Express Briefs;2018-03

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