A dividerless reference-sampling RF PLL with −253.5dB jitter FOM and <-67dBc Reference Spurs
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/8304413/8310156/08310282.pdf?arnumber=8310282
Cited by 25 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A Low Power Dual-Band Sub-Sampling Phase Locked Loop with sub-100 fs RMS Jitter and <-255-dB FOMjitter;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06
2. A Low Jitter and Low Reference Spur 5GHz PLL with Quadrature Charge-sampling PD in 28nm CMOS Process;IEICE Electronics Express;2024
3. A low jitter sub‐sampling phase‐locked loop with sampling thermal noise cancellation technique;International Journal of Circuit Theory and Applications;2022-08-22
4. A 5-GHz Sub-Sampling Phase-Locked Loop With Pulse-Width to Current Conversion;2022 International Symposium on VLSI Design, Automation and Test (VLSI-DAT);2022-04-18
5. Benchmark Figure of Merit Extensions for Low Jitter Phase Locked Loops Inspired by New PLL Architectures;IEEE Access;2022
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