A low jitter sub‐sampling phase‐locked loop with sampling thermal noise cancellation technique-Reference-Cited by-同舟云学术

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A low jitter sub‐sampling phase‐locked loop with sampling thermal noise cancellation technique

Published:2022-08-22 Issue:1 Volume:51 Page:67-79
ISSN:0098-9886
Container-title:International Journal of Circuit Theory and Applications
language:en
Short-container-title:Circuit Theory & Apps

Author:

Li Zhen¹^ORCID,Li Zhenrong¹,Wang Xudong²,Wang Zeyuan¹^ORCID,Zhuang Yiqi¹

Affiliation:

1. School of Microelectronics Xidian University Xi'an Shaanxi China

2. The 54th Research Institute of CETC Shijiazhuang Hebei China

Funder

Natural Science Basic Research Program of Shaanxi Province

State Key Laboratory of Millimeter Waves

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1002/cta.3414

Reference26 articles.

1. YangZS ChenY YangSH et al.A 25.4‐to‐29.5 GHz 10.2mW isolated sub‐sampling PLL achieving −252.9 dB jitter‐power FoM and −63 dBc Reference Spur. In: 2019 IEEE International Solid‐State Circuits Conference (ISSCC). pp. 270–272.

2. An ultra‐low power and low jitter frequency synthesizer for 5G wireless communication and IoE applications;Bagheri M;Int J Circ Theor Appl,2021

3. A Self-Calibrated 16-GHz Subsampling-PLL-Based Fast-Chirp FMCW Modulator With 1.5-GHz Bandwidth

4. A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS

5. A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit With High Speed Feed Forward Correction in 65 nm CMOS

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