Benchmark Figure of Merit Extensions for Low Jitter Phase Locked Loops Inspired by New PLL Architectures-Reference-Cited by-同舟云学术

Benchmark Figure of Merit Extensions for Low Jitter Phase Locked Loops Inspired by New PLL Architectures

Published:2022 Issue: Volume:10 Page:80680-80694
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Bae Woorham¹^ORCID

Affiliation:

1. Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA, USA

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science,Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/6287639/9668973/09847207.pdf?arnumber=9847207

Reference163 articles.

1. A pulse-position-modulation phase-noise-reduction technique for a 2-to-16 GHz injection-locked ring oscillator in 20 nm CMOS;chien;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2014

2. A 28 GHz hybrid PLL in 32 nm SOI CMOS;ferriss;Proc Symp VLSI Circuits,2013

3. 2.5 GHz 5.4 mW 1-to-2048 digital clock multiplier using a scrambling TDC;nandwana;Proc Symp VLSI Circuits,2013

4. A wideband fractional-N ring PLL with fractional-spur suppression using spectrally shaped segmentation

5. A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing;lee;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2013

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