A 5-GHz Sub-Sampling Phase-Locked Loop With Pulse-Width to Current Conversion
Author:
Affiliation:
1. National Chung Hsing University,Department of Electrical Engineering,Taichung City 402,Taiwan (R.O.C)
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9768045/9768046/09768063.pdf?arnumber=9768063
Reference12 articles.
1. High-frequency CML clock dividers in 0.13-/spl mu/m CMOS operating up to 38 GHz
2. A 2.8–4.3GHz wideband fractional-N sub-sampling synthesizer with ?112.5 dBc/Hz in-band phase noise;bajestan;IEEE Radio Frequency Integrated Circuits Symp (RFIC),2016
3. A 2.4-GHz 500-µW 370-fsrms Integrated Jitter Sub-Sampling Sub-Harmonically Injection-Locked PLL in 90-nm CMOS
4. A dividerless reference-sampling RF PLL with −253.5dB jitter FOM and <-67dBc Reference Spurs
5. A Sub-Sampling PLL with Robust Operation under Supply Interference and Short Re-Locking Time
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