A Low Jitter and Low Reference Spur 5GHz PLL with Quadrature Charge-sampling PD in 28nm CMOS Process
Author:
Affiliation:
1. National University of Defense Technology
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Link
https://www.jstage.jst.go.jp/article/elex/advpub/0/advpub_21.20240375/_pdf
Reference32 articles.
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3. [3] J. Kim, et al.: “A 16-to-40 Gb/s quarter-rate NRZ/PAM4 dualmode transmitter in 14 nm CMOS,” ISSCC Dig. Tech. Papers(2015) 1 (DOI: 10.1109/ISSCC.2015.7062925).
4. [4] W. Han, et al.: “A 56-Gbps PAM4 amplitude-rectification-based receiver with threshold adaptation and 1-tap DFE, ” IEICE Electronics Express 18 (2021) 20210302 (DOI: 10.1587/elex.18.20210302).
5. [5] K. Zhu, et al.: “A 25Gb/s RX front-end with multi-stage linear equalizer and 3-tap speculative DFE in 65nm CMOS technology, ” IEICE Electronics Express 20 (2023) 20220527 (DOI: 10.1587/elex.19.20220527).
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