Buried Power Rails and Nano-Scale TSV: Technology Boosters for Backside Power Delivery Network and 3D Heterogeneous Integration
Author:
Affiliation:
1. Imec, vzw,CMOST Department,Leuven,Belgium
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9816066/9816372/09816590.pdf?arnumber=9816590
Reference12 articles.
1. Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node
2. Extreme Wafer Thinning and nano-TSV processing for 3D Heterogeneous Integration
3. High-Aspect-Ratio Ruthenium Lines for Buried Power Rail
4. Direct Bonding of low Temperature Heterogeneous Dielectrics
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