Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node-Reference-Cited by-同舟云学术

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Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node

Published:2021-12-11 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE International Electron Devices Meeting (IEDM)
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Author:

Chen R.¹,Sisto G.¹,Jourdain A.¹,Hiblot G.¹,Stucchi M.¹,Kakarla N.¹,Chehab B.¹,Salahuddin S. M.¹,Schleicher F.¹,Veloso A.¹,Hellings G.¹,Weckx P.¹,Milojevic D.¹,Van der Plas G.¹,Ryckaert J.¹,Beyne E.¹

Affiliation:

1. IMEC,Leuven,Belgium

Funder

European Commission

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9720433/9720494/09720528.pdf?arnumber=9720528

Reference8 articles.

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. 3D backside integration of FinFETs: Is there an impact on LF noise?;Solid-State Electronics;2023-09

2. Stress Migration of Aluminum Backside Interconnect in Xtacking®;2023 IEEE International Reliability Physics Symposium (IRPS);2023-03

3. Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails;IEEE Transactions on Electron Devices;2022-12

4. A Review of the Gate-All-Around Nanosheet FET Process Opportunities;Electronics;2022-11-03

5. Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection;Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding;2022-11-03

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