Toward High Performance SiGe Channel CMOS: Design of High Electron Mobility in SiGe nFinFETs Outperforming Si
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8601505/8614478/08614581.pdf?arnumber=8614581
Cited by 15 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Hybrid Integration of Gate-All-Around Stacked Si Nanosheet FET and Si/SiGe Super-Lattice FinFET to Optimize 6T-SRAM for N3 Node and Beyond;IEEE Transactions on Electron Devices;2024-03
2. A novel approach to Si0.5Ge0.5 channel FinFET fabrication: utilizing a three-layer SiGe strain relaxation buffer and In-Situ phosphorus doping;Journal of Materials Science: Materials in Electronics;2024-02
3. Si Interlayers Trimming Strategy in Gate-All-Around Device Architecture for Si and SiGe Dual-Channel CMOS Integration;IEEE Transactions on Electron Devices;2023-12
4. Development and Analysis of a Three-Fin Trigate Q-FinFET for a 3 nm Technology Node with a Strained-Silicon Channel System;Nanomaterials;2023-05-18
5. NH3 PDA Temperature-Impact on Low-Frequency Noise Behavior of Si0.7Ge0.3 pFinFETs;IEEE Transactions on Electron Devices;2022-12
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