Si Interlayers Trimming Strategy in Gate-All-Around Device Architecture for Si and SiGe Dual-Channel CMOS Integration-Reference-Cited by-同舟云学术

Si Interlayers Trimming Strategy in Gate-All-Around Device Architecture for Si and SiGe Dual-Channel CMOS Integration

Published:2023-12 Issue:12 Volume:70 Page:6163-6168
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Zhao Fei¹^ORCID,Li Yan²,Li Yongliang¹^ORCID,Jia Xiaofeng¹,Xiong Wenjuan¹,Kong Zhenzhen¹,Luo Huaizhi²^ORCID,Li Junjie¹,Zhang Jiayi¹,Mao Xiaotong¹,Wu Zhenhua¹^ORCID,Xu Min³,Luo Jun¹^ORCID,Wang Wenwu¹

Affiliation:

1. Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China

2. School of Applied Science, Beijing Information Science and Technology University, Beijing, China

3. School of Microelectronics, Fudan University, Shanghai, China

Funder

National Natural Science Foundation of China

Strategic Priority Research Program of Chinese Academy of Sciences

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/10328902/10304674.pdf?arnumber=10304674

Reference27 articles.

1. Gate-All-Around Strained Si0.4Ge0.6 Nanosheet PMOS on Strain Relaxed Buffer for High Performance Low Power Logic Application

2. SiGe and Si Gate-All-Around FET Fabricated by Selective Etching the Same Epitaxial Layers

3. Critical Elements for Next Generation High Performance Computing Nanosheet Technology

4. Structural and Electrical Demonstration of SiGe Cladded Channel for PMOS Stacked Nanosheet Gate-All-Around Devices

5. Investigation on selectively etched SiGe and Si surface for Gate-All-Around CMOS devices fabrication

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