Structural and Electrical Demonstration of SiGe Cladded Channel for PMOS Stacked Nanosheet Gate-All-Around Devices-Reference-Cited by-同舟云学术

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Structural and Electrical Demonstration of SiGe Cladded Channel for PMOS Stacked Nanosheet Gate-All-Around Devices

Published:2020-06 Issue: Volume: Page:
ISSN:
Container-title:2020 IEEE Symposium on VLSI Technology
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Author:

Mochizuki S.,Colombeau B.,Zhang J.,Kung S. C.,Stolfi M.,Zhou H.,Breton M.,Watanabe K.,Li J.,Jagannathan H.,Cogorno M.,Mandrekar T.,Chen P.,Loubet N.,Natarajan S.,Haran B.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9264988/9264985/09265097.pdf?arnumber=9265097

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Modeling of Negative Bias Temperature Instability (NBTI) for Gate-All-Around (GAA) Stacked Nanosheet Technology;2024 IEEE International Reliability Physics Symposium (IRPS);2024-04-14

2. New structure transistors for advanced technology node CMOS ICs;National Science Review;2024-01-05

3. Multiphysics Simulation of Self-Heating-Induced Thermal Stress Effects on Quantum Transport in Gate-All-Around Nanosheet Field Effect Transistors;IEEE Transactions on Electron Devices;2024

4. Si Interlayers Trimming Strategy in Gate-All-Around Device Architecture for Si and SiGe Dual-Channel CMOS Integration;IEEE Transactions on Electron Devices;2023-12

5. NSFET performance optimization through SiGe channel design - A simulation study;Microelectronics Reliability;2023-09

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