Development and Analysis of a Three-Fin Trigate Q-FinFET for a 3 nm Technology Node with a Strained-Silicon Channel System

Abstract

Multi-gate field effect transistors (FETs) such as FinFETs are severely affected by short-channel effects (SCEs) below 14 nm technology nodes, with even taller fins incurring fringing capacitances. This leads to performance degradation of the devices, which inhibits further scaling of nanoFETs, deterring the progress of semiconductor industries. Therefore, research has not kept pace with the technological requirements of the International Roadmap for Devices and Systems (IRDS). Thus, the development of newer devices with superior performances in terms of higher ON currents, acceptable leakage currents and improved SCEs is needed to enable the continuance of integrated circuit (IC) technologies. The literature has advocated integration of strained-silicon technology in existing FinFETs, which is highly effective in enhancing ON currents through the strain effect. However, the ON currents can also be amplified by intensifying the number of fins in trigate (TG) FinFETs. Thus, three-fin TG quantum (Q)-FinFETs, using a novel tri-layered strained-silicon channel, are deployed here at 10 nm and 8 nm channel lengths. Threshold voltage is calculated analytically to validate the designs. The electrical parameters and quantum effects of both devices are explored, analysed and compared with respect to existing heterostructure-on-insulator (HOI) FinFETs and the proposed existing standard requirement of IRDS 2022 for a 3 nm technology node. The comparisons demonstrated a significant increase in the drive currents upon employing three fins of the same dimensions (8 nm gate length) and specifications in a device-based system. The performance is augmented in contrast to the 3 nm technology node device of IRDS 2022, with SCEs within the limits. Thus, employing a tri-layered strained-silicon channel system in each fin allowed for forming a three-fin Q-FinFET that, in our opinion, is the technique for consolidating the performance of the devices and enabling future generation device for faster switching operation in a sub-nano regime.