The Optimization and Analysis of a Triple-Fin Heterostructure-on-Insulator Fin Field-Effect Transistor with a Stacked High-k Configuration and 10 nm Channel Length

Abstract

The recent developments in the replacement of bulk MOSFETs with high-performance semiconductor devices create new opportunities in attaining the best device configuration with drive current, leakage current, subthreshold swing, Drain-Induced Barrier Lowering (DIBL), and other short-channel effect (SCE) parameters. Now, multigate FETs (FinFET and tri-gate (TG)) are advanced methodologies to continue the scaling of devices. Also, strain technology is used to gain a higher current drive, which raises the device performance, and high-k dielectric material is used to minimize the subthreshold current. In this work, we used stacked high-k dielectric materials in a TG n-FinFET with three fins and a 10 nm channel length, incorporating a three-layered strained silicon channel to determine the short-channel effects. Here, we replaced the gate oxide (SiO2) with a stacked gate oxide of 0.5 nm of SiO2 with a 0.5 nm effective oxide thickness of different high-k dielectric materials like Si3N4, Al2O3, ZrO2, and HfO2. It was found that the use of strained silicon and replacing only the SiO2 device with the stacked SiO2 and HfO2 device was more beneficial to obtain an optimized device with the least leakage and improved drive currents.