Hybrid Integration of Gate-All-Around Stacked Si Nanosheet FET and Si/SiGe Super-Lattice FinFET to Optimize 6T-SRAM for N3 Node and Beyond-Reference-Cited by-同舟云学术

Hybrid Integration of Gate-All-Around Stacked Si Nanosheet FET and Si/SiGe Super-Lattice FinFET to Optimize 6T-SRAM for N3 Node and Beyond

Published:2024-03 Issue:3 Volume:71 Page:1776-1783
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Zhang Xuexiang¹^ORCID,Yao Jiaxin¹^ORCID,Luo Yanna¹^ORCID,Cao Lei¹^ORCID,Zheng Yantong¹,Zhang Qingzhu¹^ORCID,Wu Zhenhua¹^ORCID,Yin Huaxiang¹^ORCID

Affiliation:

1. Integrated Circuit Advanced Process R&D Center and State Key Laboratory of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China

Funder

Strategic Priority Research Program of Chinese Academy of Sciences

Beijing Natural Science Foundation

Project funded by China Postdoctoral Sciences Foundation

Youth Innovation Promotion Association, Chinese Academy of Sciences

Science and Technology program of Beijing Municipal Science and Technology Commission

NSFC

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/16/10457976/10419223.pdf?arnumber=10419223

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1. 24.2 A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue

2. 15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications

3. Performance and design considerations for gate-all-around stacked-NanoWires FETs

4. Power aware FinFET and lateral nanosheet FET targeting for 3 nm CMOS technology;Yakimets

5. Power-performance Trade-offs for Lateral NanoSheets on Ultra-Scaled Standard Cells