Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3nm-Reference-Cited by-同舟云学术

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Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3nm

Published:2017-12 Issue: Volume: Page:
ISSN:
Container-title:2017 IEEE International Electron Devices Meeting (IEDM)
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Author:

Weckx P.,Ryckaert J.,Putcha V.,De Keersgieter A.,Boemmels J.,Schuddinck P.,Jang D.,Yakimets D.,Bardon M. G.,Ragnarsson L.-A.,Raghavan P.,Kim R. R.,Spessot A.,Verkest D.,Mocuta A.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8255107/8268301/08268430.pdf?arnumber=8268430

Cited by 19 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. BS-PDN Implemented the Latest Logic Devices for 14 Angstrom Technology Node;IEEE Transactions on Electron Devices;2024-07

2. A New Design of Ultra-Scaled and High-Density 1-nm Node 6T-SRAM Cell by Lateral-and-Complementary FETs (LC-FETs) with only 21 F²;2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA);2024-04-22

3. Self-Heating and Process-Induced Threshold Voltage Aware Reliability and Aging Analysis of Forksheet FET;2024 IEEE International Reliability Physics Symposium (IRPS);2024-04-14

4. Device Design and Reliability of GAA MBCFET;2024 IEEE International Reliability Physics Symposium (IRPS);2024-04-14

5. Compact Physics Hot-Carrier Degradation Model Valid over a Wide Bias Range;Micromachines;2023-10-30

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