Device Design and Reliability of GAA MBCFET
Author:
Affiliation:
1. Semiconductor R&D Center and Innovation Center, Samsung Electronics,Hwangsung City,Korea,445–701
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10529283/10529298/10529401.pdf?arnumber=10529401
Reference23 articles.
1. A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI
2. A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors
3. A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects
4. Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications
5. True 7nm Platform Technology featuring Smallest FinFET and Smallest SRAM cell by EUV, Special Constructs and 3rd Generation Single Diffusion Break
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