Self-Heating and Process-Induced Threshold Voltage Aware Reliability and Aging Analysis of Forksheet FET
Author:
Affiliation:
1. Indian Institute of Technology,Roorkee,India
2. Indian Institute of Technology Bhubaneswar
Funder
IIT Roorkee
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10529283/10529298/10529473.pdf?arnumber=10529473
Reference10 articles.
1. Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3nm
2. Simulation Comparison of Hot-Carrier Degradation in Nanowire, Nanosheet and Forksheet FETs
3. Investigating Nanowire, Nanosheet and Forksheet FET Hot-Carrier Reliability via TCAD Simulations: Invited Paper
4. Trap and self-heating effect based reliability analysis to reveal early aging effect in nanosheet FET
5. Self-Heating Aware Threshold Voltage Modulation Conforming to Process and Ambient Temperature Variation for Reliable Nanosheet FET
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